Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

ABSTRACT

A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

FIELD OF THE INVENTION

This invention relates to the field of semiconductor manufacture and,more particularly, to a method for forming features at a startingfeature density with a lithography mask, and resulting in a finaldensity which is n times of the first density, where n is an integergreater than 1, through the use of various conformal layers andselective etches.

BACKGROUND OF THE INVENTION

During the formation of a semiconductor device, many features such asword lines, digit lines, contacts, and other features are commonlyformed over a semiconductor wafer. A goal of semiconductor deviceengineers is to form as many of these features in a given area aspossible to increase yields, decrease manufacturing costs, and tominiaturize devices. The formation of these structures on asemiconductor wafer typically requires the use of lithography. Opticallithography, the lithographic method most used in leading-edge waferprocessing, comprises projecting coherent light of a given wavelength,typically 248 nanometers (nm) or 193 nm, from an illumination source(illuminator) through a quartz photomask or reticle having a chromepattern representative of features to be formed, and imaging thatpattern onto a wafer coated with photoresist. The light chemicallyalters the photoresist and enables the exposed photoresist (if positiveresist is used) or the unexposed photoresist (if negative resist isused) to be rinsed away using a developer.

With decreasing feature sizes, the limits of optical lithography arecontinually being tested. Improvements in feature density are madethrough process advances, enhanced lithographic methods referred to asresolution enhancement techniques, and improved equipment and materials.

One such process advance, depicted in FIGS. 1-6, uses a mask havingrepeating features of a given pitch (i.e. a given distance from thebeginning of one repeating feature to the beginning of the next feature)along with the formation of various layers and selective etches todouble the density of the features formed from the lithography mask.FIG. 1 depicts a semiconductor wafer substrate assembly 10 comprising asemiconductor wafer, a layer to be etched 12, for example a siliconnitride layer, a support layer 14, for example formed from carbon usingchemical vapor deposition (CVD) or a spin-on technique, and a patternedmasking layer 16, such as a photoresist layer formed using an opticallithographic process or a hard mask layer formed using opticallithography and an etch process. The patterned masking layer 16 may beformed at the feature size limits allowed by the lithographic process,and comprises three individual features (three periods/pitches) formedover a given distance 18.

After forming the structure of FIG. 1, an etch of the support layer 14is performed using mask 16 as a pattern. This etch is typically ananisotropic dry etch which etches the support layer 14 selective to thelayer to be etched 12 (i.e. which removes the support layer 14 withlittle or no etching of the layer to be etched 12). After etching thesupport layer 14, the patterned masking layer 16 is removed and aconformal hard mask layer 20, for example silicon dioxide, is formed toresult in the structure of FIG. 2.

Subsequently, a spacer etch of the FIG. 2 structure is performed toresult in the structure of FIG. 3 having spacers 20′ from the hard masklayer along sidewalls of the support layer 14. Subsequently, the supportlayer 14 is etched to result in the structure of FIG. 4.

Next, spacers 20′ formed from the hard mask layer are used as a patternto etch the layer to be etched 12, which results in the structure ofFIG. 5. Finally, spacers 20′ are etched selective to the layer to beetched 12 to result in the structure of FIG. 6.

The process of FIGS. 1-6 has the advantage of using optical lithographyto form the masking layer 16 having three features in a given distance18, while the completed structure depicted in FIG. 6 has six features 12(six periods/pitches) in the original distance 18. Thus the number offeatures within the distance is approximately doubled without requiringan additional lithography mask.

Various techniques to increase feature density are described in U.S.Pat. No. 5,328,810 by Tyler A. Lowrey, et al. and U.S. Pat. No.5,254,218 by Ceredig Roberts et al., both of which are assigned toMicron Technology, Inc. and incorporated herein as if set forth in theirentirety.

A method for forming a semiconductor device using an optical lithographymask with a first pitch and resulting in features having a second pitchequal to 1/n, where n is an integer greater than 1 and withoutlimitation of feature size reduction or spacing to one-half of thatattainable using lithography, would be desirable.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-6 are cross sections depicting a conventional process fordoubling the number of mask features, for example formed usingphotolithography;

FIGS. 7-15 are cross sections of an in-process semiconductor devicedepicting an embodiment of the inventive method which increases thenumber of features in a given area by four times;

FIGS. 16-22 are cross sections depicting an embodiment of the inventivemethod which increases the number of features in a given area by sixtimes;

FIGS. 23-31 are cross sections depicting another embodiment andvariations of the inventive method which increases the number offeatures in a given area by three times;

FIGS. 32-38 are cross sections depicting another embodiment of theinvention which increases the number of features in a given area by fivetimes;

FIG. 39 is an isometric depiction of various components which may bemanufactured using devices formed with an embodiment of the presentinvention; and

FIG. 40 is a block diagram of an exemplary use of the invention to formpart of a memory device having a storage transistor array.

It should be emphasized that the drawings herein may not be to exactscale and are schematic representations. The drawings are not intendedto portray the specific parameters, materials, particular uses, or thestructural details of the invention, which may be determined by one ofskill in the art by examination of the information herein.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

The term “wafer” is to be understood as a semiconductor-based materialincluding silicon, silicon-on-insulator (SOI) or silicon-on-sapphire(SOS) technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. Furthermore, when reference is made to a“wafer” in the following description, previous process steps may havebeen utilized to form regions or junctions in or over the basesemiconductor structure or foundation. Additionally, when reference ismade to a “substrate assembly” in the following description, thesubstrate assembly may include a wafer with layers including dielectricsand conductors, and features such as transistors, formed thereover,depending on the particular stage of processing. In addition, thesemiconductor need not be silicon-based, but may be based onsilicon-germanium, silicon-on-insulator, silicon-on-sapphire, germanium,or gallium arsenide, among others. Further, in the discussion and claimsherein, the term “on” used with respect to two layers, one “on” theother, means at least some contact between the layers, while “over”means the layers are in close proximity, but possibly with one or moreadditional intervening layers such that contact is possible but notrequired. Neither “on” nor “over” implies any directionality as usedherein. The term “about” indicates that the value listed may be somewhataltered, as long as the alteration does not result in nonconformance ofthe process or structure in question to the present invention. A“spacer” indicates a layer, typically dielectric, formed as a conformallayer over uneven topography then anisotropically etched to removehorizontal portions of the layer and leave taller, vertical portions ofthe layer.

Various embodiments of the present invention use alternating spacerdeposition (ASD) for pitch reduction to achieve variable criticaldimension (CD) reduction ratios. The pitch reduction process achieves aCD which is smaller than that defined by a previously formedphotolithography mask. The various process embodiments described hereincomprise the use of a first type of spacer material used as asacrificial layer and removed with high selectivity to a second spacermaterial which is used to pattern an underlying layer. Depending uponthe trim ratio, the number of spacer depositions, and the thickness ofeach deposition, a CD which is 1/n of the original value defined byprior photolithography may be achieved, where n is an odd or eveninteger greater than 1. In other words, the process multiplies thepattern density by n times. Particularly, by repeating the ASD processfollowed by a corresponding spacer etch m times, a CD may be achievedwhich is either ½m or 1/(2m−1) of the starting CD, depending upon whichof two methodologies is performed.

A first embodiment of an inventive method for forming a semiconductordevice is depicted in FIGS. 7-14. This process embodiment results in aCD which is reduced to ½m of its original value. The value of m may bedetermined by totaling the number of spacer layers formed during the ASDprocess.

FIG. 7 depicts a sacrificial photolithographic pattern 70, for examplecomprising segmented sections of photoresist having cross sectionalsidewalls, overlying a layer to be etched 72. The layer to be etched 72may be a semiconductor wafer, a semiconductor wafer substrate assemblycomprising one or more layers overlying a semiconductor wafer or wafersection, or one or more other layers which are to be subjected to apatterning etch. In this embodiment, the photolithographic features 70are formed at the lithographic limits, with the width of each feature 70and the spacing 14 between the features 70 all being about equal. Layer70 may comprise a patterned material other than photoresist.

After forming the FIG. 7, structure a trim is performed on thephotoresist using an isotropic etch to result in the structure of FIG.8. When using photoresist as layer 70, the trim may be performed byexposing mask 70 to an oxygen-based plasma such as an O₂/Cl₂ plasma oran O₂/HBr plasma. In this embodiment, the trim of the photoresist layer70 is targeted to narrow the width of each feature 70 by 0.25 (25%).That is, after trimming, the width of each feature is narrowed by about25% from the width of the pretrimmed feature. In an alternative toperforming a trim for this and other embodiments specifying a trimprocess, the photoresist features 70 may be instead printed directlyaccording to the dimensions of FIG. 8 if the lithographic process issufficiently relaxed to allow the patterning directly without a trim.The completed mask is targeted to have four times the density of theoriginal pattern, with the original pattern being the untrimmedphotoresist layer 70 at FIG. 7. As the target is to form a patterndensity which is four times the original pattern (i.e. to have a pitchwhich is ¼ of the original), the number of required spacer layersindicated by ½m is 2.

Next, a first spacer layer 90, such as silicon dioxide, is depositedover the surface of the FIG. 8 structure to result in the structure ofFIG. 9. The thickness of first spacer layer 90 is targeted to be 0.25times the width of original pattern 70 of FIG. 7. With FIG. 9, distance92 is the same as the width of each trimmed photoresist feature 70. Aspacer etch is performed on first spacer layer 90 of FIG. 9 usingconventional technology to result in the FIG. 10 structure having firstspacers 90′.

After the spacer etch of first spacer layer 90 to form spacers 90′, thephotoresist layer 70 is removed, for example using an ashing processfollowed by a wafer clean to result in the FIG. 11 structure. As thisprocess removes very little or none of the first spacers 90′, thespacing at 110 and at 92 does not change significantly.

Next, a second spacer layer 120 is formed over the FIG. 11 structure toresult in the FIG. 12 structure. The material of second spacer layer 120is selected such that first spacers 90′ may be removed selective tolayer 120 (i.e. spacer layer 90′ may be removed with little or noetching of layer 120). In this embodiment, second spacer layer 120comprises silicon nitride. This layer 120 is also targeted to athickness equal to 0.25 times the thickness of the original untrimmedphotoresist features. As spacing 110 and 92 of FIG. 11 are about equal,spacing 122 and 124 of FIG. 12 are also about equal.

After forming the FIG. 12 structure, an etch such as a spacer(anisotropic) etch is performed on the second spacer layer 120 to resultin the structure of FIG. 13 having second spacers 120′. First spacers90′ are then removed selective to second spacers 120′ to result in theFIG. 14 structure. Silicon dioxide may be removed selective to siliconnitride using a wet process such as buffered hydrofluoric acid (HF) or adry etch process known in the art. In this embodiment, the patternformed by remaining second spacers 120′ has a density which is fourtimes that of the original layer 70 at FIG. 7 (i.e. the pitch is 0.25times that of the pitch of the features of FIG. 7). The particular etchused to remove first spacers 90′ selective to second spacers 120′depends on the material used for each layer, and may be any suitableetch known in the art. Finally, the layer to be etched 72 is etchedusing the spacers 120′ as a pattern to form features from the layer tobe etched 72. Any etchant may be used which removes layer 72 withreasonable selectivity to spacers 120′ and results in a completedstructure similar to that of FIG. 15.

For this embodiment, the sizes of various elements related to thepattern formed may be described in mathematical terms. Referring to FIG.7, each sacrificial photoresist feature 70 is formed to an arbitrarywidth of 1, with the distance 14 between each feature 70 also being 1;thus, the pitch is 2. Each photoresist feature 70 is trimmed by X toresult in the structure of FIG. 8. Thus each feature 70 has a width of1−X, and the distance 14 between each feature is 1+X. In thisembodiment, where each feature 70 has a width of 1, X is equal to 0.25(i.e. 25% of the width of feature 70). Next, the first spacer layer 90is formed to have a thickness of “a,” so that distance 92 equals1+X−2am, where m is the number of spacer layers formed thus far in theprocess (i.e. 1). In this embodiment, and in other embodiments whichreduce the CD to ½m of the starting CD, “a” (the thickness of firstspacer layer 90) is targeted to be equal to X (the width trimmed fromeach feature 70). The etch of first spacer layer 90 to result in theFIG. 10 structure does not change the relationship between elements 70or 90. The removal of photoresist features 70 to result in FIG. 11 formsopening 110 having a width of 1−X (0.75), which was the post-trimmedwidth of photoresist feature 70, and a distance 92 of 1+X−2am. (Since“a” equals X and m equals 1 at this point, 1−X=1+X−2am so the twodistances 110 and 92 are equal, not counting any process-inducedvariations.) At FIG. 12, the second spacer layer 120 is formed to have athickness of “a” (again, with this embodiment, “a” is equal to X). Thusdistance 122 is equal to 1−X−2a(m−1) where m is the number of spacerlayers formed thus far (i.e. 2). Next, the second spacer layer 120 isetched to result in the FIG. 13 structure, and the first spacer layer 90is removed to result in the structure of FIG. 14.

With the original (pretrimmed) width of photoresist 70 at FIG. 7 beingequal to 1, the distance between each feature in FIG. 14 is equal to0.25. As described in the paragraph above, distance 122 is equal to1−X−2a(m−1) where, for this embodiment, X=a=0.25 and m=2 (the number ofspacer layers). Thus it may be determined that distance 122 is equal to1−0.25−2(2−1)0.25=0.25. Further, distance 124 is equal to 1+X−2am, thusit may be determined that distance 124 is equal to1+0.25−2(0.25)(2)=0.25. In general terms, “a”, the first and secondspacer layer thickness, is equal to X (the amount of trim), and alsoequal to ½m (the final CD, where “m” equals the number of spacerlayers).

It is contemplated that the process described above may be modified forhigher values of m in the expression ½m, which will increase the featuredensity by multiples of 2. A process where m=3 is depicted in FIGS. 7and 16-22, which decreases the feature pitch by ⅙ (i.e. the featuredensity is increased by six times). Again, for simplicity ofexplanation, the width of the photoresist is initially targeted to anarbitrary thickness of 1, with a distance between the photoresist of 1.The photoresist features, therefore, have a pitch of 2, which isdepicted in FIG. 7. After forming the FIG. 7 structure, each photoresistfeature 70 is trimmed by ⅙ of its width (i.e. X=⅙). Thus the distancebetween photoresist features 70 increases to 7/6.

Next, a blanket first spacer layer 160, for example silicon nitride, isformed over the trimmed photoresist as depicted in FIG. 16. Thethickness of the first spacer layer 160 is targeted to a thickness of ⅙.In FIG. 16, photoresist 70 has a width 162 of ⅚, and distance 164 isalso equal to ⅚. The first spacer layer 160 is spacer etched to resultin the first spacers 160′ as depicted in FIG. 17. The base width of eachspacer 160′ is targeted to remain at ⅙. Spacer layer 160 represents m=1,being the first spacer layer.

After forming the FIG. 17 structure, the photoresist 70 is removed and ablanket second spacer layer 180 is formed over the first spacers 160′ asdepicted in FIG. 18. Spacer layer 180 represents m=2, being the secondspacer layer. The second spacer layer 180 is formed from a materialwhich may be etched selective to first spacers 160′, for example silicondioxide. The second spacer layer 180 is targeted to a thickness of ⅙,thus distance 182 is equal to 3/6 (i.e. X/2). The FIG. 18 structure issubjected to a spacer etch of layer 180 to form second spacers 180′ asdepicted in FIG. 19, then a blanket third spacer layer 190 is formed asdepicted. The third spacer layer 190 may be formed from the samematerial as the first spacer layer, for example silicon nitride, and istargeted for a thickness of ⅙. Thus distance 192 is ⅙. Spacer layer 190represents m=3, the final spacer layer in ½m where m=3.

A spacer etch of layer 190 is performed to result in the structure ofFIG. 20 comprising spacers 160′, 180′, and 190′, then the second spacers180′ are etched and removed selective to the first spacers 160′ and tothe third spacers 190′. After the etch of the silicon dioxide secondspacers 180′ selective to silicon nitride spacers 160′ and 190′, thestructure of FIG. 21 remains. The spacers 160′, 190′ provide a maskhaving a density which is six times the density of the photoresist layer70 of FIG. 7. Finally, the layer to be etched 72 is etched using spacers160′, 190′ as a mask to result in the structure of FIG. 22.

This process may be modified from the description herein for any valueof m. The practical limit to the maximum value of m depends on theprocessing technology and the starting dimensions of X (the width of thephotoresist and the distance between the photoresist) at FIG. 7.

For a total spacer deposition of m times, the spacers obtained from(m−1)th, (m−3)th, (m−5)th, etc. depositions are sacrificial and may beselectively removed. For the embodiment of FIGS. 16-22 where m=3, them−1 spacers, i.e. the second spacers 180′, are sacrificial and areremoved. For this disclosure, the term “sacrificial” refers to spacersor other layers used in patterning (such as layer 70) which may beremoved prior to patterning the layer to be etched.

With the embodiment above providing a CD reduction of ½m where m is thenumber of spacer layers formed, the decrease in pitch is a multiple of 2(i.e. ½, ¼, ⅙, etc.). The embodiment described below provides a CDreduction of 1/(2m−1) where m≧2, thus the reduction may be ⅓, ⅕, 1/7,etc. of the original pattern.

In this embodiment, the structure of FIG. 7 is formed according totechniques known in the art, and comprises a layer to be etched 72 and aphotolithographic pattern comprising photoresist 70 overlying the layerto be etched 72. The layer to be etched may be a semiconductor wafer,one or more layers overlying a semiconductor layer, or one or more otherlayers which are to be subjected to a patterning etch. In thisembodiment, the photolithographic features 70 are formed at thelithographic limits, with the width of each feature 70 and the spacing14 between the features 70 all being about equal. Layer 70 may comprisea patterned material other than photoresist.

After forming the FIG. 7 structure, a first spacer layer 230, such assilicon dioxide, is deposited over the surface of the FIG. 7 structureto result in the structure of FIG. 23. The thickness of first spacerlayer 230 is targeted to be ⅓ times the width of photoresist 70. Aspacer etch is performed on first spacer layer 230 of FIG. 23, then thephotoresist layer 70 is removed, which results in the FIG. 24 structurehaving spacers 230′. As the spacer etch and photoresist etch removesvery little or none of the vertical portions of the first spacer layer230, the spacing at 232 and 240 does not change significantly. Spacing240 equals the width of the photoresist layer 70 depicted in FIG. 23.

Next, a second spacer layer 250 is formed over the FIG. 24 structure toresult in the FIG. 25 structure. The material of second spacer layer 250is selected such that first spacers 230′ may be removed selective tolayer 250. In this embodiment, second spacer layer 250 comprises siliconnitride. This layer 250 is also targeted to a thickness equal to ⅓ timesthe thickness of photoresist layer 70 depicted in FIG. 23. The processthus far results in spacing 232 being about ⅓ the width of photoresistlayer 70 depicted in FIG. 23. Because layer 250 is formed to have athickness (equal ⅓) which is more than ½ the distance of 232 (equal to⅓), layer 250 bridges across the openings at 232, but does not bridgeacross the openings at 240.

After forming the FIG. 25 structure, an etch such as a spacer etch isperformed on the second spacer layer 250 to result in the structure ofFIG. 26 comprising spacers 230′ and 250′. This etch exposes the layer tobe etched 72, but only at locations 260 over which photoresist layer 70was originally formed. Further, locations 260 are each only about ⅓ thewidth of the photoresist layer 70 at FIG. 23.

After forming the FIG. 26 structure, the first spacers 230′ are etchedselective to the second spacers 250′ to result in the structure of FIG.27. In this embodiment, the pattern formed by remaining second spacerlayer 250 has a density which is three times that of layer 70 at FIG. 23(i.e. the pitch is ⅓ times that of the pitch of features 70 at FIG. 23).The particular etch used to remove the first spacers 230′ selective tothe second spacers 250′ depends on the material used for each layer, andmay be any suitable etch known in the art. Finally, layer to be etched72 is etched using any etchant which removes layer 72 (removal notdepicted) with reasonable selectivity to spacers 250′.

Instead of performing a spacer etch on the FIG. 25 structure to resultin the FIG. 26 structure, a planarization process such as CMP processmay be performed on the FIG. 25 structure to result in the structure ofFIG. 28. Spacers 230′ are then removed to leave the pattern of FIG. 29,then an etch back (spacer etch) of spacer layer 250 is performed toresult in the FIG. 30 structure comprising spacers 250′. Finally, layer72 is etched to result in the structure of FIG. 31. This CMP process mayresult in spacers 250′ comprising a more uniform height than using aspacer etch, which may be advantageous to subsequent processing. As aspacer etch is performed on the FIG. 29 structure to clear thehorizontal portions of layer 250 which connect adjacent spacers, all offeatures 250′ depicted by FIG. 30 are spacers, and comprise planarized,coplanar tops.

In an alternate embodiment to the previous paragraph, an etch back oflayer 250 of FIG. 28 may be performed first, then spacers 230′ may beremoved.

The process of FIGS. 23-27 provides a CD reduction of 1/(2m−1) where m=2(comprising spacer layers 230 and 250); thus the pitch reduction is ⅓(three times the feature density). This process may be modified for anypractical value of m, thus the reduction may be ⅓, ⅕, 1/7, etc. of theoriginal pattern. A process is depicted below where m=3, thus the pitchwill be ⅕ of the original mask (i.e. five times the feature density).Again, for simplicity of explanation, the width of the photoresist isinitially targeted to an arbitrary thickness of 1, with a distancebetween the photoresist of 1. The photoresist features, therefore, havea pitch of 2, which is depicted in FIG. 7. As with the embodiment ofFIGS. 23-27, the photoresist is not trimmed in this embodiment.

For this embodiment, a blanket spacer layer, for example siliconnitride, is formed over the FIG. 7 structure. The blanket spacer layeris targeted to have a thickness of ⅕ the width of each photoresistfeature 70. A spacer etch is performed on the first spacer layer toleave the structure of FIG. 32 having first spacers 320, photoresist 70,and the layer to be etched 72. At this point, m=1, with spacers 320being formed from the first spacer layer.

Photoresist layer 70 is removed and a second spacer layer 330 is formedover the first spacers 320 as depicted in FIG. 33. Layer 330 comprises amaterial which may be etched selective to the material of spacers 320,for example silicon dioxide. Layer 330 is targeted to a thickness of ⅕,thus the spacing at 332 is ⅗ and the spacing at 334 is ⅕. A spacer etchis performed to result in the structure of FIG. 34 having first spacers320 and second spacers 330′; thus m=2 at this point in the process, withspacers 330′ being formed from the second spacer layer 320.

Next, a third spacer layer 350 is formed. Third spacer layer 350 maycomprise the same material of the first spacer layer, in this embodimentsilicon nitride, or a different material which will withstand an etch ofthe second spacer layer. The third spacer layer is targeted to athickness of ⅕. Because the target thickness of the third spacer layer350 is more than half the spacing at 334, layer 350 bridges acrossopening 334, but forms conformally at spacing 332, which has a distanceof ⅗. As there have been three spacer layers used to this point in theprocess, m=3.

After completing the FIG. 35 structure, a spacer etch is performed onthe third spacer layer 350 to result in the structure of FIG. 36 havingthird spacers 350′.

Subsequently, the second spacers 330′ are etched selective to firstspacers 320 and third spacers 350′ to result in the FIG. 37 structure.The remaining spacers 320, 350 are then used as a mask to etch the layerto be etched 72 to result in the structure of FIG. 38. Finally, spacers320, 350′ may be removed.

In the alternative to using spacer etches, a planarization, for exampleCMP, may be performed on structures of the various embodiments. This CMPprocess may result in each of the spacers having a uniform height, whichmay be advantageous to subsequent processing. Using a planarizingprocess rather than a spacer etch to remove a portion of the spacerlayer may be advantageous when using higher values of m. Rather thanhaving the profile of FIG. 38 which is formed using spacer etches, astructure formed using a planarizing process will have a profile similarto FIG. 31. It is also contemplated that one or more spacer etches maybe combined with one or more planarizing processes.

As with the embodiments depicted in FIGS. 7-22, the sizes of variouselements related to the pattern formed by the embodiments of FIGS. 23-38may be described in mathematical terms. The CD is reduced to 1/(2m−1) ofits original value, where the original value of the CD is the width ofphotoresist feature 70 at FIGS. 23 and 32, and m is the number of spacerlayers which are formed, where m≧2. The equation 1+X+2ma=−a may be usedto determine the number of spacer layers required for a given reductionin CD, where m≧2 and “a” is the thickness of the spacer layers dividedby the width of the original photoresist layer. In this embodiment, X=0as there is no trim.

While the original mask layer 70 is trimmed in the embodiments of FIGS.7-22 and untrimmed in the embodiments of FIGS. 23-38, the two processeshave similarities. For example, it is possible (but not required) toform all the spacers from only two different types of materials. The m,m−2, m−4, etc. spacer layers may all be formed from the same material,while the m−1, m−3, m−5, etc. layers may also be formed from the samematerial (but different than, and etchable selective to, the m, m−2,m−4, etc. layers). Each spacer layer is formed from a different materialthan the preceding spacer. Further, the original masking layer, layer 70in both embodiments, is removed prior to forming the second spacerlayer. Also, with either embodiment the m−1, m−3, m−5, etc. spacerlayers may be removed, while the m, m−2, m−4, etc. spacer layers may beused as a pattern.

The embodiments of FIGS. 7-22 provide a feature density multiplier whichis an even number, while the embodiments of FIGS. 23-38 provide afeature density multiplier which is an odd number. The embodiments ofFIGS. 7-22 have no bridging of the spacer layers, while the embodimentsof FIGS. 23-38 both have an instance of bridging of a spacer layer (at232 of FIG. 25 and at 334 of FIG. 35).

In yet another embodiment, the structure of FIG. 14 is formed, and layer120 is used in place of photoresist layer 70 of FIG. 7. Thus layer 120is trimmed, and a spacer layer is formed and spacer etched, then layer120 is removed, as is done in FIGS. 8-11. The process continues with thesecond spacer layer of FIGS. 12 and 13.

In another embodiment, the structure of FIG. 27 is formed, and layer 250is used in place of photoresist layer 70 of FIG. 7. Thus a spacer layeris formed over layer 250, then layer 250 is removed as is done to layer70 in FIG. 24 and this final spacer layer is used as a mask to etchlayer 10. A similar process may be performed with other embodimentsdisclosed herein.

As depicted in FIG. 39, a semiconductor device 390 formed in accordancewith the invention may be attached along with other devices such as amicroprocessor 392 to a printed circuit board 394, for example to acomputer motherboard or as a part of a memory module used in a personalcomputer, a minicomputer, or a mainframe 396. The microprocessor and/ormemory devices may be formed with (or otherwise comprise) an embodimentof the present invention. FIG. 39 may also represent use of device 390in other electronic devices comprising a housing 396, for exampledevices comprising a microprocessor 392, related to telecommunications,the automobile industry, semiconductor test and manufacturing equipment,consumer electronics, or virtually any piece of consumer or industrialelectronic equipment.

The processes and structures described herein may be used to manufacturea number of different structures comprising a patterned layer formedaccording to the inventive process. FIG. 40, for example, is asimplified block diagram of a memory device such as a dynamic randomaccess memory having container capacitors, transistor gates, and otherfeatures which may be formed using an embodiment of the presentinvention. The general operation of such a device is known to oneskilled in the art. FIG. 40 depicts a processor 392 coupled to a memorydevice 390, and further depicts the following basic sections of a memoryintegrated circuit: control circuitry 400; row address buffer 402;column address buffer 404; row decoder 406; column decoder 408; senseamplifier 410; memory array 412; and data input/output 414.

While this invention has been described with reference to illustrativeembodiments, this description is not meant to be construed in a limitingsense. Various modifications of the illustrative embodiments, as well asadditional embodiments of the invention, will be apparent to personsskilled in the art upon reference to this description. For example, thestructures described as being formed from photoresist may be formed fromother materials such as amorphous carbon (AC), transparent carbon (TC),multilayer resist (MLR), or bilayer resist (BLR). A dry development etchmay be performed to transfer a pattern from a photoresist layer to adielectric anti-reflective coating (DARC), or to a bottomanti-reflective coating (BARC), then to amorphous carbon, transparentcarbon, an underlying multilayer resist, or to an underlayer ofmultilayer resist or bilayer resist. Further, a trim, if employed, maybe performed on photoresist prior to the dry development etch or on anunderlying layer after the dry development etch.

The spacer thickness in various embodiments is assumed to be equal tothe target CD. The result is that the lines and spaces have equalwidths. However, the spacer thickness of the two types of spacermaterials may be different so that a final pattern with various dutycycles may be formed, as long as the sum of the two spacer thickness isequal to the final pitch. For example, during the pitch triple reductionprocess, a thick first spacer may be used with a thin second spacer.After the first spacer is selectively removed, the final pattern ofrelaxed pitch (i.e. the line smaller than the spacer) is formed with adensity of three times the original density. This may be preferred insome embodiments, for example when used with a shallow trench isolationprocess. It is, therefore, contemplated that the appended claims willcover any such modifications or embodiments as fall within the truescope of the invention.

1. A method used during fabrication of a semiconductor device,comprising: providing a layer to be etched; forming a sacrificialpatterning layer over the layer to be etched, wherein the sacrificialpatterning layer comprises a plurality of segmented portions having atleast first and second cross sectional sidewalls; forming a plurality ofsacrificial first spacers, with one spacer formed on each sidewall ofeach segmented portion of the sacrificial patterning layer; removing thesacrificial patterning layer; forming a conformal second spacer layerover the plurality of sacrificial first spacers; removing a portion ofthe conformal second spacer layer to form a plurality of second spacerson the sacrificial first spacers; subsequent to forming the secondspacers, removing the sacrificial first spacers; and etching the layerto be etched using the second spacers as a pattern.
 2. The method ofclaim 1 wherein each portion of the sacrificial patterning layercomprises a first width, and the method further comprises: trimming thefirst width of each sacrificial patterning layer to have a second widthwhich is about 25% narrower than the first width; forming each of theplurality of first spacers to have a width which is about 25% of thefirst width; and etching the conformal second spacer layer such that thesecond spacers each have a width which is about 25% of the first width.3. The method of claim 2 further comprising etching the layer to beetched to form features from the layer to be etched, wherein eachfeature formed from the layer to be etched comprises a width which isabout 25% of the first width.
 4. The method of claim 3 furthercomprising: forming the plurality of segmented portions of thesacrificial layer to have a pretrimmed pitch of about twice the firstwidth; and etching the layer to be etched to form the features to have apitch which is about 25% of the pretrimmed pitch of the segmentedportions of the sacrificial layer.
 5. The method of claim 1 furthercomprising: forming the sacrificial patterning layer such that theplurality of segmented portions have a first density; and etching thelayer to be etched using the second spacers as a pattern to form aplurality of features, wherein the plurality of features have a seconddensity which is about four times the first density.
 6. The method ofclaim 1 wherein each portion of the sacrificial patterning layercomprises a first width, and the method further comprises: forming eachof the plurality of first spacers to have a width which is about 33% ofthe first width; etching the conformal second spacer layer such that thesecond spacers each have a width which is about 33% of the first width.7. The method of claim 6 further comprising etching the layer to beetched to form features from the layer to be etched, wherein eachfeature formed from the layer to be etched comprises a width which isabout 33% of the first width.
 8. The method of claim 7 furthercomprising: forming the plurality of segmented portions of thesacrificial layer to have a predetermined pitch of about twice the firstwidth; and etching the layer to be etched to form the features to have apitch which is about 33% of the predetermined pitch of the segmentedportions of the sacrificial layer.
 9. The method of claim 1 furthercomprising: forming the sacrificial patterning layer such that theplurality of segmented portions have a first density; and etching thelayer to be etched using the second spacers as a pattern to form aplurality of features, wherein the plurality of features have a seconddensity which is about three times the first density.
 10. The method ofclaim 1 further comprising forming the sacrificial patterning layer fromphotoresist.
 11. The method of claim 1 further comprising forming thesacrificial patterning layer from a material selected from the groupconsisting of transparent carbon, multilayer resist, and bilayer resist.12. A method used during fabrication of a semiconductor device,comprising: providing a layer to be etched; forming a sacrificialpatterning layer over the layer to be etched, wherein the sacrificialpatterning layer comprises a plurality of segmented portions each havinga starting width which is about the same, an original pitch which isabout twice the starting width, first and second cross sectionalsidewalls, and a starting feature density; selecting a desired featurereduction using the relationship ½m, where “m” is an integer greaterthan or equal to 2 and the completed feature density will be about 2mtimes the starting feature density and the completed feature pitch willbe about ½m times the original pitch; trimming the width of eachsegmented portion of the sacrificial first patterned layer by an amountabout ½m times the starting width; forming a plurality of first spacers,with one spacer formed on each of the first and second sidewalls andeach spacer having a target width about equal to ½m times the startingwidth; removing the sacrificial patterning layer; forming a conformalsecond spacer layer on the plurality of first spacers; removing aportion of the conformal second spacer layer to form a plurality ofsecond spacers on the first spacers; subsequent to removing the portionof the conformal second spacer layer: if “m” is an even number, removingthe first spacers such that the second spacers remain; or if “m” is anodd number, removing the second spacers such that the first spacersremain; and etching the layer to be etched using the remaining spacersas a pattern.
 13. The method of claim 12 further comprising: selecting“m” to be an even number; removing the first spacers such that thesecond spacers remain; and etching the layer to be etched using at leastthe second spacers as a pattern.
 14. The method of claim 13 furthercomprising: selecting the desired feature reduction to be ½m, where “m”is 2 such that the completed feature density is about 4 times thestarting feature density and the completed feature pitch is about ¼times the original pitch; removing the first spacers such that thesecond spacers remain; and etching the layer to be etched using only thesecond spacers as a pattern.
 15. The method of claim 13 furthercomprising: selecting the desired feature reduction to be ½m where “m′is an even number greater than or equal to 4; forming a conformal thirdspacer layer over the first spacers and on the second spacers; removinga portion of the conformal third spacer layer to form third spacers;forming a conformal fourth spacer layer over the first and secondspacers and on the third spacers; removing a portion of the conformalfourth spacer layer to form fourth spacers; removing the third and firstspacers and leaving the second and fourth spacers; and etching the layerto be etched using the second and fourth spacers as a pattern.
 16. Themethod of claim 12 further comprising: selecting the desired featurereduction to be an odd number; forming a third spacer layer over thefirst spacers and on the second spacers; removing a portion of the thirdspacer layer to form third spacers; removing the second spacers andleaving the first and third spacers; and etching the layer to be etchedusing at least the first and third spacers as a pattern.
 17. The methodof claim 15 further comprising: selecting the desired feature reductionto be ½m, where “m” is 3 such that the completed feature density isabout 6 times the starting feature density and the completed featurepitch is about ⅙ times the original pitch; and etching the layer to beetched using only the first and third spacers as a pattern.
 18. A methodused during fabrication of a semiconductor device, comprising: providinga layer to be etched; forming a sacrificial patterning layer over thelayer to be etched, wherein the sacrificial patterning layer comprises aplurality of segmented portions each having a starting width which isabout the same, an original pitch which is about twice the startingwidth, first and second cross sectional sidewalls, and a startingfeature density; selecting a desired feature reduction using the formula1/(2m−1), where “m” is an integer greater than or equal to 2 and thecompleted feature density will be about (2m−1) times the startingfeature density and the completed feature pitch will be about 1/(2m−1)times the original pitch; forming a plurality of first spacers, with onefirst spacer formed on each of the first and second sidewalls and eachfirst spacer having a target width about equal to 1/(2m−1) times thestarting width; removing the sacrificial patterning layer; forming aconformal second spacer layer on the plurality of first spacers;removing a portion of the conformal second spacer layer to form aplurality of second spacers on the first spacers; subsequent to formingthe plurality of second spacers on the first spacers: if “m” is an evennumber, removing the first spacers such that the second spacers remain;or if “m” is an odd number, removing the second spacers such that thefirst spacers remain; and etching the layer to be etched using theremaining spacers as a pattern.
 19. The method of claim 18 furthercomprising: selecting “m” to be an even number; removing the firstspacers such that the second spacers remain; and etching the layer to beetched using at least the second spacers as a pattern.
 20. The method ofclaim 19 further comprising: selecting the desired feature reduction tobe 1/(2m−1), where “m” is 2 such that the completed feature density isabout 3 times the starting feature density and the completed featurepitch is about ⅓ times the original pitch; removing the first spacerssuch that the second spacers remain; and etching the layer to be etchedusing only the second spacers as a pattern.
 21. The method of claim 19further comprising: selecting the desired feature reduction to be1/(2m−1), where “m” is an even number greater than or equal to 4;forming a conformal third spacer layer over the first spacers and on thesecond spacers; removing a portion of the conformal third spacer layerto form third spacers; forming a conformal fourth spacer layer over thefirst and second spacers and on the third spacers; removing a portion ofthe conformal fourth spacer layer to form fourth spacers; removing thethird and first spacers and leaving the second and fourth spacers; andetching the layer to be etched using the second and fourth spacers as apattern.
 22. The method of claim 18 further comprising: selecting thedesired feature reduction to be an odd number; forming a third spacerlayer over the first spacers and on the second spacers; removing aportion of the third spacer layer to form third spacers; removing thesecond spacers and leaving the first and third spacers; and etching thelayer to be etched using at least the first and third spacers as apattern.
 23. The method of claim 21 further comprising: selecting thedesired feature reduction to be 1/(2m−1), where “m” is 3 such that thecompleted feature density is about 5 times the starting feature densityand the completed feature pitch is about ⅕ times the original pitch; andetching the layer to be etched using only the first and third spacers asa pattern.
 24. A method used during fabrication of an electronic system,comprising: fabricating a semiconductor device using a methodcomprising: providing a layer to be etched; forming a sacrificialpatterning layer over the layer to be etched, wherein the sacrificialpatterning layer comprises a plurality of segmented portions having atleast first and second cross sectional sidewalls; forming a plurality ofsacrificial first spacers, with one spacer formed on each sidewall ofeach segmented portion of the sacrificial patterning layer; removing thesacrificial patterning layer; forming a conformal second spacer layerover the plurality of sacrificial first spacers; removing a portion ofthe conformal second spacer layer to form a plurality of second spacerson the sacrificial first spacers; subsequent to forming the secondspacers, removing the sacrificial first spacers; and etching the layerto be etched using the second spacers as a pattern; providing amicroprocessor; and providing an electrical pathway between thesemiconductor device and the microprocessor to facilitate electricalcommunication therebetween.
 25. An in-process semiconductor device,comprising: a layer to be etched; and an etch mask comprising aplurality of planarized spacers, at least two of the spacers of theplurality comprising different materials, the spacers of the pluralityhaving coplanar upper surfaces overlying the layer to be etched.
 26. Asemiconductor device, comprising: an etched feature comprising adimension which is 1/n times a critical dimension of photolithography,where “n” is an integer greater than
 2. 27. The semiconductor device ofclaim 26, further comprising: the etched feature comprising thedimension which is 1/n times a critical dimension of photolithography,where “n” is an odd integer greater than or equal to
 3. 28. Anin-process semiconductor device comprising: a layer to be etched; and amask layer overlying the layer to be etched comprising a cross sectionhaving a plurality of separate, alternating first and second mask layerportions, wherein: the first mask layer portions each comprise a single,vertically oriented pillar; and the second mask layer portions eachcomprise a pair of vertically oriented pillars connected by ahorizontally oriented segment.
 29. The in-process semiconductor deviceof claim 28, further comprising a plurality of sacrificial spacers, withone of the plurality of sacrificial spacers interposed between eachfirst and second mask layer portion.